(a) Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit and, more particularly, to an ESD protection circuit used in a semiconductor device having a plurality of power source systems isolated from one another.
(b) Description of the Related Art
A semiconductor device (hereinafter referred to as LSI) may have a plurality of power source systems therein for use in different internal circuits. For example, in a LSI including an analog circuit and a digital circuit in a single LSI chip, separate power source lines and separate ground lines are used for the analog circuit and the digital circuit to prevent the power source voltage for the analog circuit from fluctuating due to the operations in the digital circuit, in consideration that the analog circuit is more susceptible to the voltage fluctuation.
On the other hand, in a LSI having therein a memory circuit and a CMOS buffer circuit which is capable of driving a large-capacity external load in a single LSI chip, separate power source lines and separate ground lines may be provided for the memory circuit and the CMOS buffer circuit for preventing the power source voltage of the memory circuit from fluctuating due to the voltage fluctuation caused by the buffer circuit driving the external load, in consideration that the memory circuit is more susceptible to the fluctuation of the power source voltage.
Patent Publications JPA-1988-36557 and -1998-173134 describe ESD protection circuits provided in LSIs each having a plurality of power source systems therein. FIG. 10 exemplifies a conventional ESD protection circuit provided between different power source systems and described in the above publications, illustrating an equivalent circuit diagram of the ESD protection circuit 100 provided between ground line GND1 of the power source system of a first internal circuit and ground line GND2 of the power source system of a second internal circuit of the LSI. Although not specifically shown in the publications, the layout pattern of the ESD protection circuit may be such that shown in FIG. 11, with reference to which the conventional ESD protection circuit will be described hereinafter. FIGS. 12A and 13A show sectional views taken along lines P-P′ and Q-Q′, respectively, in FIG. 11, whereas FIGS. 12B and 13B show equivalent circuit diagrams corresponding to FIGS. 12A and 13A, respectively.
The ESD protection circuit, generally designated at numeral 100, includes two diodes, diode 110 and diode 120, connected in parallel in the opposite directions. More specifically, the anode of diode 110 and the cathode of diode 120 are connected together to ground line GND1, whereas the cathode of diode 110 and the anode of diode 120 are connected together to ground line GND2. Diode 110 includes a P-well 111 formed on the main surface of a P-type silicon substrate 103 on which desired circuit elements are formed, an N-well 112 formed in the P-well 111, a heavily-doped P-type diffusion region 113 formed in the N-well 112 and connected to ground line GND1, and a heavily-doped N-type diffusion region 114 formed in the N-well 112 and connected to ground line GND2.
Diode 120 includes a P-well 121 formed on the main surface of the P-type silicon substrate 103, an N-well 122 formed in the P-well 121, a heavily-doped N-type diffusion region 124 formed in the N-well 122 and connected to ground line GND1, and a heavily-doped P-type diffusion region 123 formed in the N-well 122 and connected to ground line GND2. A heavily-doped P-type diffusion region 115 constituting a guard ring acts as a well contact for the P-well and a substrate contact for the silicon substrate 103, whereas a heavily-doped P-type diffusion region 125 acts as a well contact for the P-well 121 and a substrate contact for the silicon substrate 103.
In the configuration as described above, if an ESD stress is applied between ground line GND1 and ground line GND2, with ground line GND1 being positive with respect to ground line GND2, for example, diode 110 acts as the protection device. In this case, a forward current 11 flows from heavily-doped P-type diffusion region 113 constituting the anode of diode 110 to ground line GND2 via heavily-doped P-type diffusion region 114 constituting the cathode of diode 110, whereby a parasitic PNP transistor formed by heavily-doped P-type diffusion region 113, N-well 112 and P-well 111 is turned ON to conduct a current I2 therethrough.
On the other hand, if the ESD stress is such that ground line GND2 is positive with respect to ground line GND1, diode 120 acts as the protection device. In this case, although a forward current I1 flows from heavily-doped P-type diffusion region 123 constituting the anode of diode 120 to ground line GND1 via heavily-doped N-type diffusion region 124 constituting the cathode of diode 120, the parasitic PNP transistor formed by heavily-doped P-type diffusion region 123, N-well 122 and P-well 121 is not turned ON to cause a forward current I3 from P-well 121 to N-well 122 because P-well 121 is connected to ground line GND2 via P-well 125 constituting the well contact.
In the conventional ESD protection circuit wherein diodes are connected in parallel in the opposite directions as described above, although the parasitic PNP transistor is turned ON to form a discharge path for the ESD current as in the case of diode 110 acting as the protection device, the current gain of the parasitic PNP transistor is quite small. Thus, for assuring a sufficient ESD robustness by employing a low resistance against the ESD current, the dimensions of diodes 110 and 120 constituting the protection devices must be large. However, the larger dimensions of the diodes constituting the protection devices cause a higher parasitic capacitance between ground line GND1 and ground line GND2, which involves the problem that a high-frequency noise is more likely to transfer therebetween during a normal operation of the LSI.
In view of the above problem of the conventional ESD protection circuit, it is an object of the present invention to provide an ESD protection circuit in an LSI having a plurality of power source systems, which has a sufficient ESD robustness and is capable of suppressing a high-frequency noise from transferring between the ground lines of the power source systems during the normal operation of the LSI.